(1) Field of the Invention
This invention relates to computer systems, and, in particular, to a method and apparatus for providing multiple configuration modes to an intelligent PCI to PCI bridge.
(2) Prior Art
When a computer system is reset, a host processor of the computer system begins an initialization process. This initialization process includes initializing the values of registers to a predetermined value and also initializing the state machines to a known state. Once a host processor completes its initialization sequence, the host processor proceeds to configure the various other devices connected in the computer system.
For example, in a computer system employing a bus having a protocol, as defined by PCI Bus Protocol, the host processor configures each PCI compliant device by reading and writing the configuration registers in that device. First, the host processor reads the configuration space of each PCI compliant device to gather information concerning the device. The host then proceeds to assign the device a device number, a bus number, a portion of PCI address space, and interrupt lines.
FIG. 1 illustrates a prior art PCI compliant Intelligent Computer Add-in Card 3. This Computer Card 3 is coupled to a PCI bus slot 5 that is disposed on a backplane or a motherboard. This Computer Card 3 includes a PCI to Processor Bus Bridge that interfaces a PCI bus 9 to a Local Processor bus 11. The PCI to Local Processor Bus Bridge 7 may be implemented by the PLX 9060 chip or the V39XPCI chip. A processor 13 is coupled to the Local Processor Bus 11. This processor 13 is referred to as a "local processor" to distinguish it from the main system processor or "host processor." The Local Processor Bus 11 is also coupled to Dynamic Random Access Memory (DRAMs) and a Read Only Memory (ROM) 17 via a Memory Controller 21. The Memory Controller 21 controls accesses to the RAM 15 and the ROM 17. The Local Processor Bus 11 is also coupled to one or more input/output (I/O) devices 23 that are compliant to the protocol of the Local Processor Bus 11.
Upon system reset, the Computer Card 3 receives a P_RST# signal 25 from the host processor 27. The PCI to Local Processor Bus Bridge 7 translates the P_RST# signal 25 into a RST# signal to reset the local processor 13.
A requirement of the PCI bus protocol is that each PCI bus compliant device have a configuration space. This configuration space must include a predetermined header containing predetermined fields of information (i.e., registers that include specific information, such as, device type, vendor ID) so that the host processor, when configuring the computer system, can easily identify the PCI device and also identify its memory requirements and its processing needs.
To fulfill this requirement, the prior art includes a serial EEPROM 31 that contains the configuration information required by the PCI bus protocol. Upon receipt of the P_RST# signal 25, the configuration information stored in a serial EEPROM 31 is sent to a plurality of Configuration Registers 33 that are implemented as part of the PCI to Local Processor Bus Bridge 7.
Upon receiving the RST# signal 29, the local processor 13 begins to execute initialization software that initializes the internal registers of the local processor 13, the Memory Controller 21, Local Processor Bridge 7, and other devices in the Computer Card 3. The P-RST# signal 25 also initializes the state machines in the Computer Card 3 into a known state.
Since there are two concurrent initialization sequences occurring upon reset (i.e., the initialization for the host processor and the initialization for the local processor), a synchronization issue arises. For example, if the host processor completes its initialization sequence and begins a PCI configuration cycle before the serial EEPROM 31 downloads the pertinent information into the Configuration Registers 33 in the PCI to Local Processor Bus Bridge 7, Computer Card 3 would not be recognized by the host processor. In fact, in the prior art, there is no mechanism to guarantee that the Configuration Registers 33 are written with the appropriate information before a host processor attempts to configure the Computer Card 3. Accordingly, there is a need for a method and apparatus to guarantee that the PCI configuration space, as implemented with the Configuration Registers 33, are loaded with the appropriate information before a host processor reads these Configuration Registers 33.
Another disadvantage of the prior art is that additional board space and increased system costs for providing a serial EEPROM component 31 are incurred. This additional overhead is compounded when a computer system is configured with the components of the Computer Card 3, disposed on the baseboard or motherboard. Accordingly, a method and apparatus for guaranteeing synchronization of a reset sequence without a serial EEPROM component 31 is desirable.
Another disadvantage of the prior art is the uncertainty of synchronizing a reset sequence by streamlining the initialization software executed by the local processor 13. In other words, the prior art approach merely optimizes the initialization code that is executed by the Local Processor 13 so as to increase the probability that the local processor initialization completes before the host processor reads the configuration space of the computer card 3. As noted previously, this current approach to the synchronization problem is not a guarantee that the local processor 13 will complete its own initialization before a Host Processor 27 completes its initialization sequence. Thus, this prior art method is unpredictable and dependent on the time that the host processor requires for its initialization sequence before reading the PCI configuration registers of the Computer Card 3.
In summary, streamlining the initialization software that executes on local processor 13, so that the local processor 13 can initialize the PCI Configuration Space 33 prior to a Host Processor 27 reading the Configuration Registers, is inadequate and unpredictable since this solution is dependent on the time required by the host processor to finish its initialization sequence. Additionally, the solution of providing a serial EEPROM 31 to download information into the PCI configuration space 33 of the PCI to Local Processor Bus Bridge 7 is also inadequate and non-optimal in that the solution is still unpredictable and dependent on the initialization sequence time required by the host processor to complete initialization. This approach also incurs additional system costs and also board space.
Accordingly, there is a need for a method and apparatus for providing multi-configuration modes to an intelligent multi-function bridge.